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integrated silicon solution, inc. www.issi.com 1 rev. a 02/20/2013 copyright ? 2013 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat - est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason - ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances IS61WV51216EDALL is61/64wv51216edbll 512k x 16 high-speed asynchronous cmos static ram with ecc february 2013 features ? high-speed access times: 8, 10, 20 ns ? high-performance, low-power cmos process ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe options ? ce power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single power supply C v dd = 1.65v to 2.2v (IS61WV51216EDALL) C v dd = 2.4v to 3.6v (is61/64wv51216edbll) ? packages available: C 48-ball minibga (6mm x 8mm ) C 44-pin tsop (type ii) ? industrial and automotive temperature support ? lead-free available ? data control for upper and lower bytes description the issi IS61WV51216EDALL and is61/64wv51216edbll are high-speed, 8m-bit static rams organized as 512k words by 16 bits. it is fabri - cated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip en - able and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and read - ing of the memory. a data byte allows upper byte ( ub ) and lower byte ( lb ) access. the device is packaged in the jedec standard 44-pin tsop type ii and 48-pin mini bga (6mm x 8mm). functional block diagram m e mory l o we r i o a rra y - 512k x 8 e cc a rr a y - 512k x 4 d e c o d e r i / o d a t a circ u it ecc co l u m n i / o i o0 - 7 co n t ro l circ u it a 0 - a 1 8 i o8 - 1 5 8 ecc 8 8 8 1 2 1 2 m e mory u pp e r i o a rra y - 512k x 8 e cc a rr a y - 512k x 4 8 4 4 8 /ce /o e /w e /u b /l b
2 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll pin descriptions a0-a18 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 48-pin mini bga (6mm x 8mm) 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 nc i/o 8 ub a3 a4 ce i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 vdd vdd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 a18 a8 a9 a10 a11 nc
integrated silicon solution, inc. www.issi.com 3 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll pin descriptions a0-a18 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 44-pin tsop (type ii) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a0 a1 a2 a3 a4 ce i/o0 i/o1 i/o2 i/o3 vdd gnd i/o4 i/o5 i/o6 i/o7 we a5 a6 a7 a8 a9 a17 a16 a15 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd vdd i/o11 i/o10 i/o9 i/o8 a18 a14 a13 a12 a11 a10 pin configurations
4 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd C0.5 to v dd + 0.5 v v dd v dd relates to gnd C0.3 to 4.0 v t stg storage temperature C65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) symbol parameter conditio ns max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. truth table i/o pin mode we ce oe lb ub i/o0-i/o7 i/o8-i/o15 v dd current not selected x h x x x high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc x l x h h high-z high-z read h l l l h d out high-z i cc h l l h l high-z d out h l l l l d out d out write l l x l h d in high-z i cc l l x h l high-z d in l l x l l d in d in
integrated silicon solution, inc. www.issi.com 5 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll error detection and error correction ? independent ecc for each byte ? detect and correct one bit error per byte ? better reliability than parity code schemes which can only detect an error but not correct an error ? backward compatible: drop in replacement to current in industry standard devices (without ecc) operating range ( v dd ) r ange ambient IS61WV51216EDALL is61wv51216edbll is64wv51216edbll temperature v dd (20 n s ) v dd (8, 10 n s ) v dd (10 n s ) industrial C40c to +85c 1.65v-2.2v 2.4v-3.6v automotive (a1) C40c to +85c 2.4v-3.6v automotive (a3) C40c to +125c 2.4v-3.6v
6 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll dc electrical characteristics (over operating range) v dd = 2.4v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = C1.0 ma 1.8 v v ol output low voltage v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 2 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc ; v ih ( max.) = v dd + 2.0v a c (pulse width < 2 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 1.65v-2.2v symbol parameter test conditions min. max. unit v oh output high voltage i oh = -0.1 ma 1.4 v v ol output low voltage i ol = 0.1 ma 0.2 v v ih input high voltage 1.4 v dd + 0.2 v v il input low voltage C0.2 0.4 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , C1 1 a outputs disabled notes: 1. v il ( min.) = C0.3v d c; v il ( min.) = C1 .0v ac (pulse width < 2 ns). not 100% tested. v ih ( max.) = v dd + 0.3v d c; v ih ( max.) = v dd + 1.0v ac (pulse width < 2 ns). not 100% tested.
integrated silicon solution, inc. www.issi.com 7 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll power supply characteristics (1) (over operating range) -8 -10 -20 symbol parameter test conditions min. max. min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. 45 40 30 ma supply current i out = 0 ma, f = f max ind. 55 50 40 auto. 65 55 typ. (2) 15 i cc 1 operating v dd = max., com. 20 20 20 ma supply current i out = 0 ma, f = 0 ind. 25 25 25 auto. 50 50 i sb 1 ttl standby current v dd = max., com . 20 20 20 ma (ttl inputs) v in = v ih or v il ind. 25 25 25 ce v ih , f = 0 auto. 45 45 i sb 2 cmos standby v dd = max., com . 10 10 10 ma current (cmos inputs) ce v dd C 0.2v, ind . 15 15 15 v in v dd C 0.2v, or auto. 35 35 v in 0.2v , f = 0 typ. (2) 2 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. ac test loads figure 1. r1 5 pf including jig and scope r2 output vtm figure 2. z o = 50? vdd/2 50? output 30 pf including jig and scope ac test conditions para meter unit unit u nit (2.4v-3.6v) (3.3v + 5%) (1.65v-2.2v) input pulse level 0.4v to v dd - 0.3v 0.4v to v dd - 0.3v 0.4v to v dd - 0.3v input rise and fall times 1v/ ns 1v/ ns 1v/ ns input and output timing vdd /2 vdd + 0.05 0.9v and reference level (v ref ) 2 output load see figures 1 and 2 see figures 1 and 2 see figures 1 and 2 r1 ( ? ) 1909 317 13500 r2 ( ? ) 1105 351 10800 v tm (v) 3.0v 3.3v 1.8v
8 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll read cycle switching characteristics (1) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t rc read cycle time 8 10 ns t aa address access time 8 10 ns t oha output hold time 2.5 2.5 ns t a ce ce access time 8 10 ns t doe oe access time 5.5 6.5 ns t hzoe (2) oe to high-z output 3 4 ns t lzoe (2) oe to low-z output 0 0 ns t hzce (2 ce to high-z output 0 3 0 4 ns t lzce (2) ce to low-z output 3 3 ns t ba lb , ub access time 5.5 6.5 ns t hzb (2) lb , ub to high-z output 0 3 0 3 ns t lzb (2) lb , ub to low-z output 0 0 ns t pu power up time 0 0 ns t pd power down time 8 10 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage.
integrated silicon solution, inc. www.issi.com 9 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll read cycle switching characteristics (1) (over operating range) -20 ns symbol parameter min. max. unit t rc read cycle time 20 ns t aa address access time 20 ns t oha output hold time 2.5 ns t a ce ce access time 20 ns t doe oe access time 8 ns t hzoe (2) oe to high-z output 0 8 ns t lzoe (2) oe to low-z output 0 ns t hzce (2 ce to high-z output 0 8 ns t lzce (2) ce to low-z output 3 ns t ba lb , ub access time 8 ns t hzb lb , ub to high-z output 0 8 ns t lzb lb , ub to low-z output 0 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
10 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid address oe ce d out t hzce read cycle no. 2 (1,3) ( ce and oe controlled ) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il ) data valid previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. www.issi.com 11 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll write cycle switching characteristics (1,3) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t wc write cycle time 8 10 ns t sce ce to write end 6.5 8 ns t aw address setup time 6.5 8 ns to write end t ha address hold from write end 0 0 ns t sa address setup time 0 0 ns t pwb lb , ub valid to end of write 6.5 8 ns t pwe 1 we pulse width 6.5 8 ns t pwe 2 we pulse width ( oe = low) 8.0 10 ns t sd data setup to write end 5 6 ns t hd data hold from write end 0 0 ns t hzwe (2) we low to high-z output 3.5 5 ns t lzwe (2) we high to low-z output 2 2 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initi - ate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. shaded area product in development
12 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll write cycle switching characteristics (1,2) (over operating range) -20 ns symbol parameter min. max. unit t wc write cycle time 20 ns t sce ce to write end 12 ns t aw address setup time 12 ns to write end t ha address hold from write end 0 ns t sa address setup time 0 ns t pwb lb , ub valid to end of write 12 ns t pwe 1 we pulse width ( oe = high) 12 ns t pwe 2 we pulse width ( oe = low) 17 ns t sd data setup to write end 9 ns t hd data hold from write end 0 ns t hzwe (2) we low to high-z output 9 ns t lzwe (2) we high to low-z output 3 ns notes: 1. t est conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
integrated silicon solution, inc. www.issi.com 13 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll ac waveforms write cycle no. 1 (1,2) ( ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd
14 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll ac waveforms write cycle no. 2 ( we controlled. oe is high during write cycle) (1,2) data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd write cycle no. 3 ( we controlled. oe is low during write cycle) (1) data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd
integrated silicon solution, inc. www.issi.com 15 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll ac waveforms write cycle no. 4 ( lb , ub controlled, back-to-back write) (1,3) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha notes: 1. the internal write time is defned by the overlap of ce = lo w , ub and/or lb = lo w , and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the t sa , t ha , t sd , and t hd timing is referenced to the rising or falling edge of the signal that terminates the write. 2. tested with oe high for a minimum of 4 ns before we = low to place the i/o in a high-z state. 3. we may be held low across many address cycles and the lb , ub pins can be used to control the write function.
16 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll data retention waveform ( ce controlled) v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode data retention switching characteristics (2.4v-3.6v) symbol parameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 3.6 v i dr data retention current v dd = v dr ( min ) , ce v dd C 0.2v com. 2 10 ma ind. 15 auto. 35 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note 1 : typical values are measured at v dd = v dr ( min ) t a = 25 o c and not 100% tested. data retention switching characteristics (1.65v-2.2v) symbol parameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = v dr ( min ) , ce v dd C 0.2v com. 2 10 ma ind. 15 auto. 35 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note 1 : typical values are measured at v dd = v dr ( min ) , t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 17 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll ordering information industrial range: -40c to +85c voltage range: 2.4v to 3.6v sp eed (ns) order part no. pa ckage 8 is61wv51216edbll-8bli 48 mini bga (6mm x 8mm), lead-free is61wv51216edbll-8tli tsop (type ii), lead-free 10 is61wv51216edbll-10bi 48 mini bga (6mm x 8mm) is61wv51216edbll-10bli 48 mini bga (6mm x 8mm), lead-free is61wv51216edbll-10ti tsop (type ii) is61wv51216edbll-10tli tsop (type ii), lead-free automotive range: -40c to +125c voltage range: 2.4v to 3.6v sp eed (ns) order part no. pa ckage 10 is64wv51216edbll-10ba3 48 mini bga (6mm x 8mm) is64wv51216edbll-10bla3 48 mini bga (6mm x 8mm), lead-free is64wv51216edbll-10cta3 tsop (type ii), copper leadframe is64wv51216edbll-10ctla3 tsop (type ii), lead-free, copper leadframe industrial range: -40c to +85c voltage range: 1.65v to 2.2v sp eed (ns) order part no. pa ckage 20 IS61WV51216EDALL-20bli 48 mini bga (6mm x 8mm), lead-free IS61WV51216EDALL-20tli tsop (type ii), lead-free
18 integrated silicon solution, inc. www.issi.com rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/12/2008 package outline
integrated silicon solution, inc. www.issi.com 19 rev. a 02/20/2013 IS61WV51216EDALL is61/64wv51216edbll 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline

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